1. Field of the Invention
The present invention directs to a method of manufacturing a semiconductor device, particularly, to a method of manufacturing a semiconductor device featured in the ion implantation step and to a method of manufacturing a semiconductor device featured in the step of forming the gate electrode of a transistor.
2. Description of the Related Art
In recent years, a large scale integration (xe2x80x9cLSIxe2x80x9d), in which many transistors and resistors are connected to each other to form an electric circuit and are mounted integrally on a single chip, could be used in some portions of an electronic computer or a communication appliance. Therefore, the performance of an entire apparatus can be heavily related to the performance of the LSI single body. The performance of the LSI single body can be improved by increasing the degree of integration, i.e., by improving the elements quality of the chips.
The elements can be improved by rendering optimum the ion implantation for forming the diffusion layers, such as the source-drain diffusion layers and the annealing treatment after the ion implantation. As a result, it is possible to obtain a metal oxide semiconductor (xe2x80x9cMOSxe2x80x9d) transistor having shallow source-drain diffusion layers having a depth not larger than 0.2 xcexcm.
If ions are implanted into a silicon substrate, crystal defects can be generated in the silicon substrate. It is commonly known in the art that the crystal defects do not decrease in the subsequent heat treatment, thus causing the weakening of the mechanical strength of the silicon substrate by multiple repetitions of the ion implantation and the heat treatment process.
The silicon substrate may be cooled during the ion implantation process to avoid the problem discussed above, thereby suppressing the migration of the atomic void during the ion implantation. As a result, it is possible to permit the interstitial atom introduced by the ion implantation to be coupled with the atomic void so as to eliminate the defect.
However, if a silicon substrate is cooled to about xe2x88x92160xc2x0 C. and an ion implantation is applied to the silicon substrate by masking the region other than the region in which the ion implantation is performed with a photoresist used in an ordinary lithography, cracks 122 are generated in a resist mask 118, as shown in a cross sectional view in FIG. 1. It is commonly understood that one of the causes of a crack may be attributable to the fact that water within the photoresist was initially frozen then when submitted to heat treatment, the volume of the water expands. If cracks are generated in the resist, ions are implanted into the masked region, too, so as to deteriorate the pn junction characteristics, resulting in failure to obtain a desired atomic characteristic. In the worst scenario, cracks can also be generated in the underlying insulating film where the cracks are generated on the resist pattern. The problem is that, if a crack is generated in the photoresist, ions are implanted into an undesired region. This phenomenon will now be explained with reference to FIG. 1.
Specifically, FIG. 1 is a cross sectional view of a construction of a Complementary Metal Oxide Semiconductor-Field Effect Transistor (xe2x80x9cCMOS-FETxe2x80x9d) where an ion implantation is performed using a conventional photoresist as a mask.
The CMOS-FET shown in FIG. 1 is obtained by the following steps. In the first step, an n-type well 112, a p-type well 113, and an insulating film 114 for element isolation are formed in a semiconductor substrate 111. Then, a gate insulating film 115 is formed on the surface of the semiconductor substrate 111, followed by forming a gate or a dummy gate 116, which will be described in further detail. After formation of electrode 116, a p-type impurity layer 117 is formed by implanting ions of boron (xe2x80x9cBxe2x80x9d) or boron fluoride (xe2x80x9cBF3xe2x80x9d) into semiconductor substrate 111 in a concentration of approximately 1xc3x971014 to 5xc3x971015 cmxe2x88x922. Further, a photoresist layer is formed in a thickness of approximately 0.5 to 1.5 xcexcm, followed by applying a light exposure and development so as to obtain a photoresist pattern 118. The photoresist pattern 118 thus formed is used as a mask for forming n-type impurity layers 120.
In the next step, an n-type impurity 119 such as arsenic (xe2x80x9cAsxe2x80x9d) or antimony (xe2x80x9cSbxe2x80x9d) is implanted in a concentration of approximately 1xc3x971014 to 5xc3x971015 cmxe2x88x922 as shown in FIG. 1 while cooling the substrate and having photoresist mask 118 formed thereon to temperatures not higher than xe2x88x92150xc2x0 C. The method of manufacturing a transistor by using a photoresist mask as described has its shortcomings. Specifically, a crack 122 is generated in photoresist mask 118 in the cooling stage of semiconductor substrate 111. Therefore, n-type impurity 119 passes through crack 122 to form an n-type diffusion layer 121 in p-type impurity layer 117. As a result, the leak current through the pn junction is increased by at least two folds and, thus, it may not be possible to obtain good element characteristics.
Another method of miniaturizing the element may include using a dummy gate. In this method, a dummy gate of a laminate structure consisting of a silicon nitride film and a polycrystalline silicon (xe2x80x9cpoly-Sixe2x80x9d) film is formed first, followed by forming source-drain regions and an interlayer insulating film. Then, the surface of the dummy gate is exposed and the dummy gate is removed, followed by newly formed metal gate film. A transistor comprising a gate film formed by this method is called a damascene gate Metal Oxide Semiconductor Field Effect Transistor (xe2x80x9cMOSFETxe2x80x9d). An example of a manufacturing method of a damascene gate MOSFET will be described below.
FIGS. 2A to 2C and 3A to 3C collectively show another method of manufacturing a transistor by using a dummy gate.
In a first step, the structure shown in FIG. 2A is prepared and can be obtained as follows. Specifically, a groove is formed by dry etching on the surface of a silicon semiconductor substrate 71, followed by forming an insulating film within the groove by means of deposition or coating. It is possible to use a silicon oxide film as the insulating film. Alternatively, it is also possible to use a film of silicon nitric oxide (xe2x80x9cSiNOxe2x80x9d) having a thermal expansion coefficient close to that of silicon, i.e., about 3 ppm/K. The surface of the insulating film thus formed is polished by a chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d) method or a mechanical polishing (xe2x80x9cMPxe2x80x9d) method so as to form an insulating film 72 for element isolation.
Then, an oxide film 73 for a dummy gate is formed by thermal oxidation in a thickness of about 3 to 10 nm on an element region surrounded by insulating film 72 for element isolation, followed by forming a film for a dummy gate on oxide film 73. A laminate film consisting of a silicon nitride (xe2x80x9cSi3N4xe2x80x9d) film and an amorphous silicon film or a laminate film consisting of a silicon nitride film and a poly-Si film are used as the film for the dummy gate. The film for the dummy gate thus formed is subjected to an anisotropic etching so as to form a dummy gate 90 equal in shape to the gate. In FIG. 2A, dummy gate 90 comprises an amorphous silicon film or poly-Si film 90a and a Si3N4 film 90b. 
The particular laminate structure makes it possible to prevent the surface of the poly-Si film from being exposed to the outside in the subsequent planarizing process. As a result, it is possible to prevent the poly-Si film from performing a silicidation reaction with cobalt (xe2x80x9cCoxe2x80x9d) in the subsequent silicidation process. Incidentally, the poly-Si film is selected as a material with a large etching selectivity relative to the thin insulating film 73 so as to permit the thin insulating film 73 to perform the function of the etching stopper in the step of removing the dummy gate, i.e., in the step of removing the poly-Si film, which is carried out after the silicidation process. It is possible to use an amorphous silicon film in place of the poly-Si film.
After the formation of dummy gate 90, it is possible to increase the thickness of oxide film 73 in the source-drain regions by thermal oxidation. Then, extension regions 75 of the source-drain regions can be formed by an ion implantation method, a plasma doping method, or a gaseous phase diffusion method with dummy gate 90 as a mask. Further, an electrical activation is achieved by applying a heat treatment at 800xc2x0 C. to 900xc2x0 C. for 30 seconds or less by employing Rapid Thermal Annealing (xe2x80x9cRTAxe2x80x9d) in which the temperature can be elevated at a rate of at least approximately 100xc2x0 C./sec.
In the subsequent step, the structure as shown in FIG. 2B is prepared. In the first step, a side wall insulating film 76 consisting of a silicon nitride film or a silicon oxynitride film is formed on the side wall of dummy gate 90 in a thickness of approximately 5 to 30 nm. Then, deep source-drain regions 77 are formed in silicon semiconductor substrate 71 by employing an ion implantation method, a plasma doping method, or a gaseous phase diffusion method. Further, an electrical activation is achieved by applying a heat treatment at 800xc2x0 C. to 900xc2x0 C. for 30 seconds or less by employing an RTA in which the temperature can be elevated at a rate of at least approximately 100xc2x0 C./sec.
Then, oxide films 73 in source-drain 77 are removed by the treatment with, for example, hydrofluoric acid, followed by a silicide process for depositing on the entire surface a metal having a resistivity of about 20 xcexa9 cm or less and capable of forming a silicide so as to form a metal film. Specifically, a metal film such as a cobalt film is deposited by a sputtering method in a thickness of about 10 to 20 nm. In the case of using a metal such as cobalt that does not reduce the silicon oxide film, it is desirable to deposit a metal, such as titanium, that is capable of reducing the silicon oxide film on the cobalt film because titanium is diffused into the cobalt film in the subsequent heat treating step so as to reduce the silicon oxide film, which was not removed completely, at the interface between the cobalt film and the silicon substrate.
It is possible to form a barrier film relative to, for example, nitrogen on the entire surface in order to prevent the surface of the cobalt film or the titanium film formed thereon from being nitrided in the subsequent heat treatment performed under a nitrogen atmosphere. It is possible to use, for example, a titanium nitride (xe2x80x9cTiNxe2x80x9d) film as the barrier film.
Then, a heat treatment is applied under, for example, a nitrogen gas atmosphere. As a result, only cobalt deposited on source-drain regions 77 to perform a silicide-forming reaction so as to form selectively only a mono-silicide layer on source-drain regions 77.
The temperature of the heat treatment can be determined depending on the kind of the metal deposited. For example, if cobalt is deposited, mono-silicide of cobalt is formed by the heat treatment of about 500xc2x0 C. However, when cobalt is deposited on element isolating insulating film 72, side wall insulating film 76 and silicon nitride film 90b in the upper portion of dummy gate 90 does not perform a silicide-forming reaction and cobalt remains unreacted. The unreacted cobalt can be selectively removed by using, for example, a mixed solution consisting of sulfuric acid and hydrogen peroxide solution. As a result, cobalt mono-silicide layers are selectively formed only on source-drain regions 77 and, then, a heat treatment is applied at about 800xc2x0 C. so as to permit the cobalt mono-silicide layers 78a to react with silicon and, thus, forming cobalt disilicide layers 78b, as shown in FIG. 2C, thereby finishing the silicide process.
In the next step, an interlayer insulating film 79, such as a silicon oxide film, is formed by, for example, a Chemical Vapor Deposition (xe2x80x9cCVDxe2x80x9d) method. It is possible to form the interlayer insulating film after depositing a thin film capable of suppressing the diffusion of cobalt, such as a silicon nitride film with a thickness of about 20 nm.
Further, as a planarizing process, the surface of interlayer insulating film 79 is planarized by, for example, a CVD method so as to expose the surface of silicon nitride film 90b formed on dummy gate 90, as shown in FIG. 3A, followed by removing silicon nitride film 90b by a treatment with a hot phosphoric acid so as to expose silicon film 90a, as shown in FIG. 3B.
In the next step, silicon film 90a is removed by a chemical dry etching performed by using a carbon tetrafluroide/oxygen (xe2x80x9cCF4/O2xe2x80x9d) mixed gas, followed by removing thin oxide film 73 positioned below dummy gate 90 by treatment with diluted hydrofluoric acid, diluted ammonium fluoride or a mixed solution thereof so as to form an open portion 90xe2x80x2, as shown in FIG. 3C.
Then, an oxide film 81 having a thickness not larger than 1 nm is formed on the surface of open portion 90xe2x80x2, as shown in FIG. 4, followed by depositing an insulating film 82 having a relative dielectric constant larger than that of a silicon oxide film and a metal conductive film 83. Insulating film 82 can be formed of, for example, tantalum oxide (xe2x80x9cTa2O5xe2x80x9d), titanium dioxide (xe2x80x9cTiO2xe2x80x9d), zirconium oxide (xe2x80x9cZrO2xe2x80x9d), hafnium oxide (xe2x80x9cHfO2xe2x80x9d) or ceric oxide (xe2x80x9cCeO2xe2x80x9d). On the other hand, metal conductive film 83, which determines the work function of the gate, can be formed in a thickness not larger than 10 nm by using, for example, a metal nitride. Further, a film of a metal having a low resistivity such as aluminum (xe2x80x9cAlxe2x80x9d) or tungsten (xe2x80x9cWxe2x80x9d) is deposited on the surface of metal conductive film 83. The metal film is planarized by CMP or MP and etched so as to finish formation of a gate 84, as shown in FIG. 4.
However, an additional problem is generated in the case of using a dummy gate. Specifically, a damascene gate MOSFET is a transistor of high performance as compared to a MOSFET, but requires a long manufacturing process. If calculated by raw process time (xe2x80x9cRPTxe2x80x9d), the manufacturing process is about 22 hours longer, when compared with another method of manufacturing a transistor. The reason for the difficulty is that, in the manufacture of a damascene gate MOSFET, about 20 hours is required for forming a dummy gate consisting of a silicon nitride (xe2x80x9cSi3N4xe2x80x9d) film and a poly-Si film, and requires about 2 hours for removing the particular structure with phosphoric acid or a mixed gas consisting of CF4 and O2. What should also be noted is that, since the poly-Si film has a columnar crystal structure, an irregularity is formed on the side surface of the dummy gate. Since the width of the dummy gate is determined in view of the irregularity noted above, the processing accuracy of the gate size is poor. Incidentally, even if an amorphous silicon film is used in place of the poly-Si film, the amorphous silicon film is converted into a poly-Si film in the heat treating step and, thus, the problem remains unsolved.
In the method described above, an ion implantation is performed through oxide film 73 for forming extension regions 75 of the source-drain regions. It is desirable to carry out the ion implantation without causing the ions not to be implanted through oxide film 73 in order to achieve the junction depth not larger than 30 nm in the extension regions. However, it is impossible to carry out the ion implantation in this fashion because the problem described below is brought about in the dummy gate structure consisting of a silicon nitride film and a poly-Si film. Specifically, where oxide films 73 on the source-drain regions are removed after the dummy gate formation, shown in FIG. 2A, by the treatment with hydrofluoric acid diluted with water, oxide film 73 below the lower poly-Si film 90a constituting the dummy gate is partly removed, as shown in FIG. 5. This means that the lower oxide film 73 acting as an etching stopper is removed. It follows that, when poly-Si film 90a acting as the dummy gate is removed by etching, an etched region 91 of silicon substrate 71 is formed, as shown in FIG. 6, resulting in the impossibility of forming a transistor.
The disadvantages inherent in the prior art can be summarized as follows:
1. If a photoresist is cooled, cracks are generated. Therefore, ions are implanted into undesired regions of the silicon substrate, with the result that the pn junction characteristics of the element are deteriorated. In the worst case, cracks are also generated in the insulating film positioned below the photoresist mask.
2. The silicon nitride film and the poly-Si film (or amorphous silicon film) collectively constitutes a dummy gate which is formed by a CVD method, and is removed by a method using phosphoric acid or a mixed gas of CF4 and O2, leading to a long RPT. Also, since the poly-Si film has a columnar crystal structure, an irregularity is formed on the side surface of the dummy gate, leading to poor accuracy in processing of the gate size.
3. Since the silicon substrate does not exhibit an etching selectivity relative to the dummy gate, it is impossible to remove the oxide film on the silicon substrate until the dummy gate is completely removed. As a result, ions are implanted into the silicon substrate through the oxide film, making it impossible to form a shallow layer in the extended portion. Such being the situation, it was impossible to achieve miniaturization.
An object of the present invention is to provide a method of manufacturing a semiconductor device, in which a desired ion implantation is applied to a desired region of a semiconductor substrate so as to ensure good pn junction characteristics and, thus, to improve markedly the element characteristics.
Another object of the present invention is to provide a method of manufacturing a semiconductor device by using a dummy gate, in which an RPT can be markedly shortened and the working accuracy of the gate size improved.
According to the first objective, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of:
forming a polymer film pattern in a predetermined region of a semiconductor substrate having a gate electrode or a dummy gate formed thereof with an insulating film interposed therebetween; and
implanting ions into the semiconductor substrate using the polymer film pattern as a mask while cooling the semiconductor substrate;
wherein the polymer film pattern is formed by the steps comprising:
coating the semiconductor substrate with a polymer having a proportionally larger amount of carbon for forming a polymer film;
forming a photoresist pattern on the polymer film; and
transferring the pattern shape of the photoresist pattern onto the polymer film.
It is desirable for the semiconductor substrate to be cooled at temperatures not higher than 0xc2x0 C., more preferably at temperatures not higher than xe2x88x92100xc2x0 C., and most preferably at temperatures not higher than xe2x88x92150xc2x0 C.
The manufacturing method of the present invention can further comprise the step of removing the polymer film pattern after implanting ions into the semiconductor substrate, and subjecting the semiconductor substrate to a heat treatment, and removing the polymer film pattern. In this case, it is preferred for the heat treatment to be performed at temperatures not lower than 500xc2x0 C.
According to the second objective, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of:
forming a dummy gate on a semiconductor substrate;
introducing an impurity into the semiconductor substrate using the dummy gate as a mask to form at least one source-drain diffusion region;
forming and positioning an insulating film surrounding the dummy gate;
removing the dummy gate to form an opening; and
forming a gate electrode in an opening with a gate insulating film formed below the gate electrode;
wherein the dummy gate is formed by the steps comprising:
coating the semiconductor substrate with a polymer having a proportionally larger amount of carbon for forming a polymer film;
forming a photoresist pattern on the polymer film; and
transferring. the pattern shape of the photoresist pattern onto the polymer film.
The method of removing the dummy gate can be done by using an oxygen plasma or an active oxygen.
The manufacturing method of the present invention can comprise the step of oxidizing a surface layer of the source-drain diffusion region after removing the dummy gate. The manufacturing method of the present invention can also comprise the step of electrically activating the impurity by applying a heat treatment after formation of the source-drain diffusion region. In the manufacturing method of the present invention, it is desirable to carry out the process ranging between the step of forming the dummy gate and the step of removing the dummy gate under temperatures not higher than 600xc2x0 C. Heat treatment after removal of the dummy gate can be performed at least at 600xc2x0 C.
Alternatively, the manufacturing method according to the present invention can be carried out by forming a mono-silicide in a surface layer of the source-drain diffusion region, introducing a channel impurity into the surface of the semiconductor substrate where the dummy gate was removed and before the heat treatment of at least 600xc2x0 C. is carried out. In this case, at least two of the activation of the impurity introduced into the source-drain diffusion region, namely, the di-silicidation of the mono-silicide, and the activation of the channel impurity can be performed simultaneously by the heat treatment carried out at a temperature of at least 600xc2x0 C.
Additionally, the manufacturing method of the present invention can further comprise the step of forming a thin silicon oxide film on the semiconductor substrate before forming the dummy gate on the semiconductor substrate and removing the exposed region of the thin silicon oxide film before implanting an impurity into the semiconductor substrate by using the dummy gate as a mask.
It is desirable for the polymer in accordance with the present invention to have high carbon content, for manufacturing a semiconductor device, more particularly, to have a carbon content higher than that of the hydrogen content in terms of atomic ratio, preferably, there should be at least 50% of carbon by atomic ratio in the polymer. More preferably, the carbon content of the polymer should be at least 1.1 times higher than the hydrogen content and the polymer should comprise at least 55% by atomic ratio of carbon.
For manufacturing a semiconductor device in accordance with the present invention, it is preferred that the polymer film have a higher carbon content to be subjected to a heat treatment at about 600xc2x0 C. to 900xc2x0 C. and at a temperature elevation rate not higher than about 50xc2x0 C./min. It is more preferable that the temperature elevation rate be not higher than 10xc2x0 C./min.
In this disclosure, xe2x80x9ccomprisesxe2x80x9d, xe2x80x9ccomprisingxe2x80x9d and the like can have the meaning ascribed to them in U.S. Patent Law and can mean xe2x80x9cincludesxe2x80x9d, xe2x80x9cincludingxe2x80x9d and the like.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.